Define system-level power management architecture and operating modesDefine CPU and cluster power states and their coordination mechanismsDefine reset flow architecture, including cold and warm reset sequencing and reset-power state interactionsDefine PM policies, sequencing, and state transitions across the platformDefine hardware–firmware power management interfaces and compliance expectationsDefine power management requirements and constraints to guide implementation teamsAlign architecture, RTL, physical design, thermal, and firmware teams around a coherent PM strategySupport silicon bring-up and post-silicon power behavior validationRequired Experience7+ years in SoC or CPU power management architectureDirect experience with ARM CPU power management architecture, including familiarity with ARM power management specifications and compliance requirements (e.g., PSCI, ARM power state definitions,



firmware coordination models)Strong understanding of system-level power state management and hardware–firmware PM interactionSolid understanding of power delivery constraintsTrack record of cross-functional coordination across architecture, design, and firmware teamsPreferred ExperienceFamiliarity with low-power implementation flows (e.g., UPF) and physical power considerationsUnderstanding of thermal management concepts and power-thermal interaction at system levelHigh-performance or server-class CPU experienceRISC-V experienceSilicon bring-up and post-silicon tuning experienceMulti-generation architecture planning experienceApply for this positionPersonal informationFirst name Last name Email Address Phone number NationalityYour resumeYour LinkedIn Profile Upload your Resume/CV Upload File Max file size 10MB.
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📌 Power Management Architect (Jalisco)
🏢 AheadComputing
📍 Jalisco