Job Overview Intel's Central Engineering Group is seeking a DDR/LPDDR Memory Subsystem Firmware Developer to design, develop, and validate DDR and LPDDR memory reference code for next‐generation products.The role operates at the critical hardware‐software boundary, writing foundational initialization and training algorithms to ensure maximum bandwidth, strict power efficiency, and optimal signal integrity.Responsibilities Write, maintain, support, optimize, and debug low‐level firmware in C and C++ for memory initialization, configuration, and runtime management.Implement and support advanced DRAM training algorithms (e.g., write/read leveling, VREF training) in accordance with JEDEC specifications.Execute and test firmware on architectural models, test chip platforms, simulation platforms (FPGA/emulation), and RTL environments before physical silicon is available.Participate in post‐silicon bring‐up in the lab, diagnosing and resolving complex hardware/firmware integration bugs.Partner with So C architecture, analog design, validation, and DDR/LPDDR PHY IP design teams to ensure correct hardware‐software mapping.Document memory reference code specifications and user guides for OEMs and internal platform engineering teams.Develop and optimize automation scripts using C/C++ and Python, and operate advanced lab equipment (high‐speed oscilloscopes, logic analyzers, data acquisition tools).
Publish MRC validation plans and reports summarizing all validation activities, review results, and communicate findings to relevant teams.Collaborate with silicon, hardware, and software teams to deliver innovative, market‐ready solutions.Partner with customers' R&D; and manufacturing teams to address factory challenges, integrate DFx requirements,



and ensure smooth product ramp.Deliver product training and provide technical support to drive systematic improvements.Qualifications Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.5+ years total experience, including: Developing and executing test plans in a Linux/UNIX environment.Object‐oriented programming in C, C++, C#, and/or Python.Memory reference code development and debugging for DDR/LPDDR interfaces.Understanding of JEDEC standards for DDR and LPDDR (Desktop/Server, Embedded Hardware, Firmware, system bring‐up).
Experience with hardware and firmware validation test plans and test case development.Proficiency with system‐level validation and debugging of MRC issues.Experience with test automation and debugging on emulation models.Experience operating lab equipment such as logic analyzers, oscilloscopes, and protocol analyzers.Advanced English proficiency.Unrestricted, permanent right to work in Mexico (no visa or sponsorship).
Preferred Qualifications Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.Experience with memory reference code development and debugging specifically for DDR/LPDDR memory interfaces.Power‐on experience and familiarity with silicon bring‐up processes.Proficiency in Linux/UNIX development environments.Previous involvement in post‐silicon validation and product ramp support.Job Details Job Type: Experienced Hire Shift: Shift1 (Mexico) Primary Location: Mexico, Guadalajara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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📌 Ddr Phy Firmware Engineer (Jalisco)
🏢 Intel
📍 Jalisco