Soc Infrastructure/Noc, Power & Performance Validation Engineer, Staff (Tijuana)

Soc Infrastructure/Noc, Power & Performance Validation Engineer, Staff (Tijuana)

10 nov
|
QUALCOMM
|
Tijuana

10 nov

QUALCOMM

Tijuana

Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob Area:Engineering Group, Engineering Group ASICS EngineeringGeneral Summary:Qualcomm's System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases. This role focuses on content quality and system-level validation enablement, offering deep exposure to Qualcomm SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains.Premium mobile and flagship platformsData centerAI Accelerator platformRole OverviewThe team is currently seeking candidate specifically for SOC Infrastructure/NoC, Power and Performance Validation in pre-silicon emulation and post-silicon of industry-leading, next generation Premium-Tier Mobile & AI Accelerator platform.

An idóneo candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture, performance and power.Roles & ResponsibilitiesCome up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored inSOC Bandwidth, QoS, Latency and Throughput analysisMinimum RequirementsBS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science,



or related field.Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverageSolid expertise in various FIFO designs and related performance/functionality aspectsMemory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAMThorough understanding of CPU and DDR concepts, Multimedia, GPU, PeripheralsSystem low power modes, Dynamic clock and voltage scaling operations, Interrupt architectureDebug architecture - interactions with JTAG based debuggers, state dump scriptsIn depth debugging experience for Complex HW and SW issuesExperience working with Perfmon architecture -performance counters, telemetry data, and hardware/software co-optimization.Drive correlation between pre-silicon models, emulation platforms, and silicon performance measurements.Evaluate AI inference and training workloads to ensure optimal throughput, latency, memory bandwidth, and power-performance efficiency.Contribute to methodology development for performance characterization, benchmarking, and KPI tracking across product generations.Create performance dashboards,



reports, and technical reviews for leadership and cross-functional stakeholders.Experience in embedded systems/expertise in C, C++, Python and assembly languages. Design and Implementation of drivers and test contentLogical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validationFundamental understanding of Static, Leakage and Dynamic power in a semiconductor designFamiliarity in debug tools including JTAG and kernel debuggersPreferred QualificationStrong understanding of computer architecture, AI/ML accelerators, memory hierarchy, cache coherency, and on-chip interconnects.Familiarity with System level debug, silicon bring-upMinimum QualificationsBachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. #

📌 Soc Infrastructure/Noc, Power & Performance Validation Engineer, Staff (Tijuana)
🏢 QUALCOMM
📍 Tijuana

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