system validation & emulation (sve) team is part of the central so c validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .

this team focuses on content quality and system-level validation enablement , offering deep exposure to so cs through bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across hw and sw boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of so c domains.

excellent opportunity to work on cutting-edge so cs across multiple product segments , including:

- premium mobile and flagship platforms
- ai accelerator platform

role overview

seeking an experienced ddr validation engineer for end-to-end validation of next-generation lpddr5 x and lpddr6 memory subsystems on ai accelerator and flagship mobile platforms. This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

key responsibilities

- define and execute ddr validation strategy across emulation, fpga, and silicon platforms.
- drive lpddr5 x/lpddr6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement.
- develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
- lead debug of ddr controller, phy, firmware, si/pi, timing, and system-level issues.
- validate interactions between ddr, cpu, gpu, npu,



cache hierarchy, no c, and system software.
- drive bandwidth, latency, qo s, memory pressure, and ai workload characterization.
- develop scalable automation, regression infrastructure, and debug analytics frameworks.
- partner with architecture, design, firmware, si/pi, package, and dram vendors to root-cause and resolve issues.

required qualifications
- bs/ms/ph d in ee, ce, cs, or related field.
- 5+ years of experience in ddr/memory subsystem validation or silicon bring-up.
- strong understanding of:
- ddr controllers and phys
- memory training and calibration algorithms
- cache, coherency, and no c architectures
- power management and low-power memory features
- proficiency in c/c++ and low-level software development.

preferred qualifications
- mobile so c, ai compute, automotive, or server platform validation experience.
- familiarity with si/pi analysis, memory performance tuning, and thermal characterization.
- experience driving first-silicon memory bring-up and volume production qualification.

minimum qualifications
- bachelor's degree in science, engineering, or related field and 4+ years of asic design, verification, validation, integration, or related work experience.
- master's degree in science, engineering, or related field and 3+ years of asic design, verification, validation, integration, or related work experience.
- ph d in science, engineering, or related field and 2+ years of asic design, verification, validation, integration, or related work experience.

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📌 Ddr validation engineer (Tijuana)
🏢 North American Production Sharing
📍 Tijuana