soc clock & power management validation engineer, staff

tipo de empleo: permanent

tipo jornada: full-time

fecha de publicación:

identificador oferta: 62603

general summary

system validation & emulation (sve) team is part of the central so c validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .

this role focuses on content quality and system-level validation enablement , offering deep exposure to so cs through bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across hw and sw boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of so c domains.

excellent opportunity to work on cutting-edge so cs across multiple product segments , including:

- premium mobile and flagship platforms
- ai accelerator platform

role overview

system level validation of clock, power, reset, and power-management architectures for next-generation premium tier msm platforms. Drive pre-silicon and post-silicon validation of clocking infrastructure, pmic integration, dvfs, and low-power features across complex multi-die ai systems. Partner closely with architecture, design, verification & firmware teams to debug and root-cause power, performance, stability, and scalability issues. Define validation methodologies, stress workloads, and automation frameworks to ensure robust operation under demanding ai training and inference scenarios.



Own power subsystem bring-up readiness and delivery of production-quality silicon across all program milestones

an adecuado candidate combines expertise in clocking, dvfs, power management, pmic, firmware, silicon bring-up, and ai/hpc platform validation

- own the e2 e bare metal framework validation so c clock and power architectures
- validation planning – understand design changes, visualize standalone and system level test requirements and scenarios
- test plan development – clearly document test strategy and dependencies
- conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers
- develop scalable device drivers, standalone and system tests using c
- debug complex issues both on pre-si and post-si platforms, provide debug direction
- review validation platform schematics to ensure post-si debug support – might have to work with platform design team
- automate validation process – development, execution, inference using python, perl, shell
- use lab instruments – multimeter, oscilloscopes , logic analyzer
- efficiently collaborate with teams in different time zones – both internal and external




- 5+ years of relevant experience in so c validation and / or associated areas (sw development, embedded systems etc.)
- prior work experience in clock/ power validation
- proficient in c, python
- experienced in using lab instruments – multimeter, oscilloscopes , logic analyzers
- exposure to debug tools (jtag etc.). Knowledge of debug methodology of arm based so cs
- very good at problem solving - analytical and debugging skills

preferred qualifications
- prior exposure to below sw skills would add an edge above other applicants:
- experience with cross-compilers, linkers and makefiles
- understanding of coherency and concurrency in modern so c architecture
- knowledge of pmic/ prior experience in validating rail power (power measurement tools/ setups)
- knowledge of pre-silicon validation and debug on fpga based emulation platforms is a plus
- knowledge of rtl and hdls (verilog/ system verilog) would be an additional advantage
- should have prior work experience in a cross functional matrix work environment

minimum qualifications
- bachelor's degree in science, engineering, or related field and 4+ years of asic design, verification, validation, integration, or related work experience.
- master's degree in science, engineering, or related field and 3+ years of asic design, verification, validation, integration, or related work experience.
- ph d in science, engineering, or related field and 2+ years of asic design, verification, validation, integration, or related work experience.

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📌 Soc clock & power management validation engineer, staff (Tijuana)
🏢 North American Production Sharing
📍 Tijuana