Our vision is to transform how the world uses information to enrich life for all .
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies.
We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.
As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules.
You will be required to meet all engineering and process related criteria needed for an assigned Dram product.
You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution.
In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits.
You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.
Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips.




Perform layout verification like LVS/DRC/EM, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment.
Guide and lead developing team members in their execution of Sub block-level layouts we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.
Must have 3+ years of experience in layout designs in advanced CMOS process.
Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.
Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
Should have adequate knowledge of schematics, collaborate with circuit designer and CAD team.
Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.
Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL

📌 Dram Design Tech Layout Engineer (Jalisco)
🏢 Micron
📍 Jalisco