Micron Technology, Inc. in Mexico invites experienced engineers to join our DRAM Design Engineering Group.
You will translate schematics into physical IP layouts for DRAM chips, ensure on-time delivery, perform LVS/DRC checks, and collaborate with general teams across the US, India, and Japan to meet project milestones. You should have 3+ years in layout designs for advanced CMOS processes, strong knowledge of Cadence Virtuoso, and familiarity with device matching, parasitic analysis, and
#J-18808-Ljbffr
📌 DRAM Layout Design Engineer – Lead IP & Global Projects (Centro)
🏢 Micron Technology
📍 Centro
Postulate a este anuncio
Muestra tus habilidades a la empresa, rellenar el formulario y deja un toque personal en la carta, ayudará el reclutador en la elección del candidato.