DRAM Layout Design Engineer – Lead IP & Global Projects (San Pedro Tlaquepaque)

DRAM Layout Design Engineer – Lead IP & Global Projects (San Pedro Tlaquepaque)

07 nov
|
Micron Technology
|
San Pedro Tlaquepaque

07 nov

Micron Technology

San Pedro Tlaquepaque

Micron Technology, Inc. in Mexico invites experienced engineers to join our DRAM Design Engineering Group.

You will translate schematics into physical IP layouts for DRAM chips, ensure on-time delivery, perform LVS/DRC checks, and collaborate with general teams across the US, India, and Japan to meet project milestones. You should have 3+ years in layout designs for advanced CMOS processes, strong knowledge of Cadence Virtuoso, and familiarity with device matching, parasitic analysis, and

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📌 DRAM Layout Design Engineer – Lead IP & Global Projects (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque

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Recibe por email las nuevas ofertas de trabajo para: dram layout design engineer – lead ip & global projects (san pedro tlaquepaque) / san pedro tlaquepaque