Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAJob Area:Engineering Group, Engineering Group ASICS EngineeringGeneral Summary:Qualcomm's System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre
- and post-silicon phases . This team focuses on content quality and system-level validation enablement, offering deep exposure to Qualcomm SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains.
Premium mobile and flagship platformsData centerAI Accelerator platformRole OverviewWe are seeking an experienced DDR Validation Engineer for end-to-end validation of next-generation LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms. This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.
Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement.
Develop and execute validation plans covering memory functionality, performance,



reliability, power, and corner-case scenarios.
Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
Minimum RequirementsBS or MS or PhD in EE, CE, CS, or related field.
LPDDR***
* architecturesDDR controllers and PHYsMemory training and calibration algorithmsCache, coherency, and NoC architecturesPower management and low-power memory featuresStrong post-silicon debug experience.
Proficiency in C/C++ and low-level software development.
Preferred QualificationsMobile SoC, AI compute, automotive, or server platform validation experience.
Familiarity with SI/PI analysis, memory performance tuning, and thermal characterization.
Experience driving first-silicon memory bring-up and volume production qualification.
Minimum

Qualifications:
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

📌 Ddr Validation Engineer, Staff (México)
🏢 Qualcomm
📍 México