Ciena Corporation in Mexico is seeking a Senior Layout Engineer to contribute to high-speed analog/mixed-signal layout in deep-submicron CMOS processes. You will collaborate with senior designers to plan and implement layouts for DAC, ADC, PLL, and SERDES, ensuring product performance and reliability.
Strong experience with Cadence Virtuoso, Calibre, and Totem is required, along with a Bachelor's degree in Electrical Engineering and at least five years in custom analog layout.