Senior Analog Ic Layout Engineer (Jalisco)

Senior Analog Ic Layout Engineer (Jalisco)

16 oct
|
NXP Semiconductors
|
Jalisco

16 oct

NXP Semiconductors

Jalisco

About the TeamNXP Semiconductors is seeking an experienced Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS).
The Central Layout Group delivers physical implementation expertise for complex mixed-signal and power management integrated circuits supporting multiple product lines worldwide.
The team collaborates with Design, Verification, Package, Test and Product Engineering organizations across a integral R&D; network to drive the successful execution of advanced automotive and industrial semiconductor products.Role SummaryThe successful candidate will play a key role in the development of complex automotive mixed-signal and power management ICs, driving layout execution from planning through tape-out while collaborating with stakeholders across multiple worldwide engineering sites.ResponsibilitiesLayout ExecutionLead the physical implementation of Analog and Mixed-Signal integrated circuitsDefine and optimize floorplans for complex blocks and top-level assembliesDrive layout activities from planning through tape-outEnsure design quality, robustness and compliance with development methodologiesVerification and Sign-OffOwn DRC, LVS,



ERC and physical sign-off activitiesSupport extraction analysis and post-layout verificationDrive root-cause analysis and resolution of layout-related challengesTechnical LeadershipCoordinate layout activities with Design, Verification, Package, Test and Product Engineering teamsMentor junior engineers and share technical expertiseContribute to layout methodology improvements and best practicesSupport project execution through accurate planning, communication and risk managementRequirementsBachelor or Master Degree in Electrical Engineering, Electronics, Physics or MicroelectronicsStrong experience in Analog IC Layout developmentExpertise with Cadence Virtuoso Layout environmentExperience with DRC/LVS sign-off methodologiesSolid understanding of CMOS, BCD, SOI and Mixed-Signal design environmentsAbility to work independently and manage complex technical challengesStrong communication, collaboration and stakeholder management skillsFluent written and spoken EnglishPreferred QualificationsExperience with Calibre, PVS, Quantus, StarRC or equivalent EDA toolsExperience with automotive semiconductor productsKnowledge of High Voltage technologiesExperience in layout automation and scripting (SKILL, Python, TCL or Shell)Previous mentoring or technical leadership experienceExperience working in multi-site international R&D; organizationsInterest in AI-assisted engineering and design productivity solutionsMore information about NXP in Mexico...#J-*****-Ljbffr

📌 Senior Analog Ic Layout Engineer (Jalisco)
🏢 NXP Semiconductors
📍 Jalisco

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