ASICS EngineeringGeneral Summary:We are looking for talented and ambitious individuals to join the TECHIP team. The candidate should have strong IP modeling, Char tool know-how and hands-on experience and automation skills. Hands-on experience in EDA tool automation, data analysis and visualization & large-scale software automation enablement. Excellent understanding of statistical Liberty timing, power model and Front-end Verilog views and tools. Silicon reliability modeling, validation with multiple foundries & EDA house is a plus.Required for this Role:* Strong Std cell / Memory circuit knowledge & IP characterization, Design Kit delivery background.* Strong logical and problem-solving skills with excellent analytical and debugging skills* Strong Software programming skills in Python or Perl in UNIX/Linux computing platform* Highly motivated, excellent team spirit and good communication skills.* Ability to work in multi-site project teams, third party vendors to drive cutting edge tools,
flows in QCOM environment for characterization flow and sign-off methodologiesPreferred Qualifications:* In depth technical knowledge of CMOS, Fin FET logic and transistor, basic of digital circuit design optimization* Familiar with industry standard Design kit (DK) views, Liberty formats for foundation IPs (advanced modeling formats CCS, LVF) , statistical variation models & worked on development of the same.* Familiarity with front end pre-silicon design flow, RTL design/coding, logic design, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA), Design for Test, BIST modeling experience.* Expertise in scripting in Python (data-analytics), Perl & experience in developing large scale automation from scratch.* Experience in STA, physical design is a plus.* Experience of spice simulation models, design rules verification procedures (like DRC/LVS/ERC) is a plus. The adecuado candidate would also have experience with industry standard chip design tools and de