Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Job Area: ASICS Engineering
General Summary: Qualcomm's System Validation & Emulation (SVE) team is part of the central So C validation organization responsible for ensuring end-to-end silicon quality across pre-and post-silicon phases.
Excellent Opportunity to work on cutting-edge So Cs across multiple product segments, including: Premium mobile and flagship platforms Data center AI Accelerator platform Role Overview: System level validation of clock, power, reset, and power-management architectures for next-generation Premium Tier MSM platforms. Drive pre-silicon and post-silicon validation of Clocking infrastructure, PMIC integration, DVFS, and low-power features across complex multi-die AI systems. Partner closely with Architecture, Design, Verification & Firmware teams to debug and root-cause power, performance, stability, and scalability issues. Define validation methodologies, stress workloads, and automation frameworks to ensure robust operation under demanding AI training and inference scenarios.



Own power subsystem bring-up readiness and delivery of production-quality silicon across all program milestones
An adecuado candidate combines expertise in Clocking, DVFS, Power Management, PMIC, Firmware, Silicon Bring-up, and AI/HPC platform validation
Roles & Responsibilities: Own the E2 E bare metal framework validation So C clock and power architectures Validation planning – understand design changes, visualize standalone and system level test requirements and scenarios Test plan development – clearly document test strategy and dependencies Conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers Develop scalable device drivers, standalone and system tests using C Debug complex issues both on pre-Si and post-Si platforms, provide debug direction Review validation platform schematics to ensure post-Si debug sup

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