Micron Technology, Inc. in Mexico is seeking a DRAM Layout Designer to translate schematics into physical layouts for fabrication reticles.
You will optimize IP layouts for DRAM products and collaborate with design, CAD, and general engineering teams to meet quality and timing targets. The role requires strong CMOS layout fundamentals, proficiency with Cadence Virtuoso and Mentor Calibre, and experience in physical verification tasks such as DRC/LVS.
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📌 Senior DRAM Layout Engineer — Advance Memory Tech (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque
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