DDR Validation Engineer, Staff (Tijuana)

DDR Validation Engineer, Staff (Tijuana)

14 oct
|
Qualcomm
|
Tijuana

14 oct

Qualcomm

Tijuana

Company:
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA Job Area:
Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm's System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring
end-to-end silicon quality across pre- and post-silicon phases .
This team focuses on
content quality and system-level validation enablement , offering deep exposure to Qualcomm SoCs through
bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to
develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of SoC domains.
Excellent Opportunity to work on
cutting-edge SoCs across multiple product segments , including: Premium mobile and flagship platforms Data center AI Accelerator platform
Role Overview
We are seeking an experienced
DDR Validation Engineer
for end-to-end validation of next-generation
LPDDR5X and LPDDR6 memory subsystems




on AI Accelerator and Flagship mobile platforms.
This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.
Key Responsibilities Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms. Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement. Develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios. Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues. Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software. Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization. Develop scalable automation, regression infrastructure, and debug analytics frameworks. Partn

📌 DDR Validation Engineer, Staff (Tijuana)
🏢 Qualcomm
📍 Tijuana

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