Micron Technology is seeking a Layout Build engineer for the DRAM Team in Guadalajara, Mexico. You will contribute to analog/mixed-signal layout and integration for high-performance memory applications in a general team.
With around 5 years of analog layout experience, you will use Cadence VLE/VXL and Mentor Calibre to ensure LVS/DRC quality and timely delivery of layouts across multiple projects. Strong collaboration and problem-solving skills are essential.