so c infrastructure/no c, power & performance validation engineer, staff

tipo de empleo: permanent

tipo jornada: full-time

fecha de publicación:

identificador oferta: 62604

general summary:

system validation & emulation (sve) team is part of the central so c validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .

this role focuses on content quality and system-level validation enablement , offering deep exposure to so cs through bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across hw and sw boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of so c domains.

excellent opportunity to work on cutting-edge so cs across multiple product segments , including: premium mobile and flagship platforms ai accelerator platform role overview:

the team is currently seeking candidate specifically for soc infrastructure/no c, power and performance validationin pre-silicon emulation and post-silicon of industry-leading, next generation premium-tier mobile & ai accelerator platform. An idóneo candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze soc bus architecture,performance and power.

come up with thorough performance validation plans and work closely with team members to ensure performance-power trade-offs are factored in soc bandwidth, qo s,



latency and throughput analysis bs/ms/ph d in electrical engineering, computer engineering, computer science, or related field. 5+ years of experience in silicon validation, or platform bring-up. Interconnect architectures - no cs, axi, ahb etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage solid expertise in various fifo designs and related performance/functionality aspects memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, mte, mpam thorough understanding of cpu and ddr concepts, multimedia, gpu, peripherals systemlow power modes, dynamic clock and voltage scaling operations, interrupt architecture debug architecture - interactions with jtag based debuggers, state dump scripts in depth debugging experience for complex hw and sw issues experience working with perfmon architecture -performance counters, telemetry data, and hardware/software co-optimization. Drive correlation between pre-silicon models, emulation platforms, and silicon performance measurements. Evaluate ai inference and training workloads to ensure optimal throughput, latency, memory bandwidth,



and power-performance efficiency. Contribute to methodology development for performance characterization, benchmarking, and kpi tracking across product generations. Create performance dashboards, reports, and technical reviews for leadership and cross-functional stakeholders. Experience in embedded systems/expertise in c, c++, python and assembly languages. Design and implementation of drivers and test content logical thinking and problem-solving ability with focus on power, performance and so c system feature validation fundamental understanding of static, leakage and dynamic power in a semiconductor design familiarity in debug tools including jtag and kernel debuggers preferred qualification: strong understanding of computer architecture, ai/ml accelerators, memory hierarchy, cache coherency, and on-chip interconnects. Knowledge of ai/ml workloads, tensor operations, matrix multiplication, transformer models, and large-scale inference systems. Familiarity with system level debug, silicon bring-up minimum qualifications:

bachelor's degree in science, engineering, or related field and 4+ years of asic design, verification, validation, integration, or related work experience.
or
master's degree in science, engineering, or related field and 3+ years of asic design, verification, validation, integration, or related work experience.
or
ph d in science, engineering, or related field and 2+ years of asic design, verification, validation, integration, or related work experience. #j-18808-ljbffr

📌 Soc infrastructure/noc, power & performance validation engineer, staff (Tijuana)
🏢 North American Production Sharing
📍 Tijuana