Micron Technology is seeking a DRAM Layout Engineer to translate schematics into physical IP layouts for DRAM chips.
You will verify layouts, optimize area and routing, and ensure timely delivery across general teams.The role requires 3+ years of CMOS layout experience, strong problem-solving, and proficiency with Cadence Virtuoso, Calibre, and Mentor tools.
You will collaborate with design groups worldwide to meet project milestones.
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📌 Dram Layout Engineer: Design & Verification Expert (México)
🏢 Micron
📍 México