DRAM Layout Engineer Intern — CMOS (México)

DRAM Layout Engineer Intern — CMOS (México)

08 oct
|
Micron
|
México

08 oct

Micron

México

Micron Technology is seeking a student intern to develop and verify high-quality physical layouts for cutting-edge DRAM products. You will gain hands-on experience with layout building, physical verification, and industry-standard EDA tools like Cadence and Calibre under the guidance of experienced engineers.
Responsibilities include floor planning, layout design, and following verification protocols while collaborating with general teams.

📌 DRAM Layout Engineer Intern — CMOS (México)
🏢 Micron
📍 México

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