Micron is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing, and physical verification.
You will have the opportunity to develop automation solutions with scripting and AI-supported development, gaining hands-on experience with industry-standard EDA tools and advancing semiconductor memory technologies.
📌 DRAM IP Layout Intern — Automation (Jalisco)
🏢 Micron Technology
📍 Jalisco
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