HCL Technologies Limited invites a senior ASIC/SoC verification engineer with 8–14 years of hands-on experience to join our design verification team.
You will participate in multiple tapeouts, develop UVM-based testbenches, write test plans, drive functional coverage, and debug complex simulations to ensure design quality.
The role requires strong SystemVerilog, Verilog, UVM expertise, and collaboration with hardware teams.
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