DRAM Layout Engineer — Lead IP Design (Xalisco)

DRAM Layout Engineer — Lead IP Design (Xalisco)

07 oct
|
Micron
|
Xalisco

07 oct

Micron

Xalisco

Micron Technology, Inc. is seeking a senior DRAM layout engineer to translate schematics into IP layouts for DRAM chips and lead layout activities across integral teams. You will verify layouts using LVS/DRC/EM and ensure on-time delivery with quality standards.
The role requires 3+ years in CMOS layouts, strong fundamentals in layout and routing, and deep Cadence/Mentor Calibre expertise. Collaboration with CAD and circuit teams is essential, enabling high-performance memory tech.

📌 DRAM Layout Engineer — Lead IP Design (Xalisco)
🏢 Micron
📍 Xalisco

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