Micron Technology is seeking a DRAM Layout Engineer to translate schematics into physical IP layouts for DRAM chips. You will verify layouts, optimize area and routing, and ensure timely delivery across integral teams.
The role requires 3+ years of CMOS layout experience, strong problem-solving, and proficiency with Cadence Virtuoso, Calibre, and Mentor tools. You will collaborate with design groups worldwide to meet project milestones.