DRAM Layout Engineer: IP Block Design (México)

DRAM Layout Engineer: IP Block Design (México)

05 oct
|
Micron Technology
|
México

05 oct

Micron Technology

México

Micron Technology is seeking an experienced DRAM Layout Engineer to transform schematics into physical layouts for advanced CMOS processes. You will lead IP layout development, perform verification, and drive on-time delivery while coordinating with global teams across the US, India, and Japan.
Idóneo candidates have 3+ years in CMOS layouts, strong Cadence skills, and a track record of collaborative leadership in multi-project environments.

📌 DRAM Layout Engineer: IP Block Design (México)
🏢 Micron Technology
📍 México

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