Company:

qualcomm semiconductores y sistemas avanzados de baja california

job area:

asics engineering

general summary:

qualcomm's so c validation team (sve – system validation & emulation) is part of the central so c digital hardware organization responsible for the overall quality of the so c silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers to solve the toughest issues spanning board design, so c rtl, microcontroller firmware, os/software, and process variation. We are currently seeking a candidate for the position of framework developer engineer up to staff level title.

in this position you will be developing sve bare metal framework enabling global teams to effectively validate the qualcomm hw products. Through close interaction with core teams and understanding their hw validation needs, you will develop solutions to satisfy crucial project milestones on a broad range of the newest snapdragon so cs. You will be driving the development of new framework features to e.g. enable ate testing as part of the production screening process, a new initiative with a major potential for huge cost savings. If you are passionate about resolving tough technical problems, working with various global teams, and intrigued in constantly learning new technologies and applying them efficiently to your work, we’re looking for a candidate just like you!

responsibilities design, develop, debug system/ip validation framework to be used in bare-metal and light-weight-rtos environments for various so c validation activities by general core teams understand the newest snapdragon so c architecture and design features, and ensure the sve infrastructure can support various core teams to achieve planned hw validation goals interface with various ip validation and cross functional teams (design/dv/sw) to understand and debug complex issues, and to enable the sve test infrastructure on emulation and post-si environments enable new framework test flows to be used e.g. for mbist testing in the high-volume production screen flow mandatory skills: good knowledge and understanding of embedded sw architecture and content development in c/c++ for validation purposes working knowledge of armv8/armv9/x86/risc-v cpu architectures, interrupt handling, cache coherency, io coherency,



and so c architectures with complex smp/heterogenous cores understanding memory management techniques including weakly ordered memory model, pipelining of memory systems, memory barriers, etc. Working knowledge of software build toolchains comprising compilers, makefiles, linker and scatter files, etc. Previous hands‑on sw boot loader design and debug experience is highly preferred experience in optimizing code, and efficiently resolving linker issues experience in using jtag interfaces and debug tools for analyzing hw desired skills exposure to broad range of so c architecture concepts – interconnects, power management, inter-processor communication techniques, etc. Knowledge of operating systems/rtos/linux kernel internals, multithreading, scheduling policies, locking mechanism, virtual memory, mmu, etc. Working knowledge for the use of compilers and linkers such as gcc, clang, rvds, llvm bring-up of hw-sw solutions on fpga/emulation platforms and on fresh soc designs exposure to build automation tools such as jenkins, and experience in creating automated processes to streamline the development process regression testing exposure: understanding the available methodologies and tools, ability to design, implement and execute comprehensive test suites for sw quality and stability minimum requirements: 5+ years of hands‑on silicon validation and embedded sw development experience on modern cpu and so c architectures proficiency with c/c++ coding, and at least familiarity with assembly, vhdl/verilog and various scripting languages like python or perl understanding of mobile chip and/or server architecture (cpu, gpu, ddr, nocs, peripherals, etc.), and systematic debug and root‑cause techniques of low‑level sw/hw issues ability to use lab equipment for testing and validation, including logic analyzers and oscilloscopes debug tools including jtag and kernel debuggers like lauterbach trace32 good written and spoken communication skills education: required: bachelor’s, computer and/or electrical engineering preferred: master’s,



computer and/or electrical engineering minimum qualifications: bachelor's degree in science, engineering, or related field and 4+ years of asic design, verification, validation, integration, or related work experience.
or
master's degree in science, engineering, or related field and 3+ years of asic design, verification, validation, integration, or related work experience.
or
ph d in science, engineering, or related field and 2+ years of asic design, verification, validation, integration, or related work experience.

applicants: qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@ or call qualcomm's toll-free number found here. Upon request, qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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if you would like more information about this role, please contact qualcomm careers. #j-18808-ljbffr

📌 Framework developer engineer (Tijuana)
🏢 QUALCOMM
📍 Tijuana