As a Verification Engineer, you will drive pre-silicon verification activities for complex full-chip custom memory designs, including High Bandwidth Memory (HBM) and emerging memory architectures. You will own verification planning, simulation, debug, coverage improvement, and analysis efforts while collaborating with globally distributed engineering teams. This role offers the opportunity to influence verification methodologies, develop scalable solutions, and leverage AI-assisted automation to improve engineering efficiency and quality. ### Responsibilities* Lead verification activities within your area of expertise and help define verification strategy for assigned projects.* Simulate, analyze, and debug pre-silicon full-chip custom designs to identify and resolve functional issues.* Develop test cases and stimulus to improve functional coverage for HBM and emerging memory architectures and features.* Create, enhance, and maintain verification environments, testbenches, and regression suites using industry-standard simulation tools.* Collaborate with integral design and verification teams to develop new verification flows and methodologies that address emerging memory design challenges.* Execute regression testing, analyze coverage results, and drive continuous improvements in verification quality and efficiency.* Support cross-functional initiatives that broaden team capabilities and product knowledge.* Leverage AI-assisted tools and automation techniques to improve verification workflows, coverage analysis, and engineering productivity.



### Minimum Qualifications* Bachelor's degree or Master of Technology in Electronics Engineering or a related field.* 5+ years of experience in pre-silicon verification.* Experience establishing, developing, and simulating verification environments.* Understanding of digital circuit fundamentals, simulation methodologies, debugging, troubleshooting, and design evaluation.* Experience developing test cases and verification stimulus to improve functional coverage. ### Preferred Qualifications* Experience with Universal Verification Methodology (UVM).* Knowledge of Design for Testability (DFT) concepts, including custom DFT implementations and standard scan-chain architectures.* Exposure to critical timing analysis and data-path timing evaluation.* Experience owning verification and end-to-end analysis of complex full-chip custom designs with demanding power, performance, and bandwidth requirements.* Experience applying AI-enabled automation to technical or operational engineering processes."The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."
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📌 ENGINEER - HBM VERIFICATION Tlaquepaque, Jalisco, Mexico Posted a day ago (Centro)
🏢 Micron Technology
📍 Centro