Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Job Area: Engineering Group, Engineering Group > ASICS Engineering
General Summary: Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases. This role focuses on content quality and system-level validation enablement, offering deep exposure to Qualcomm SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains.
Excellent Opportunity to work on cutting-edge SoCs across multiple product segments, including: Premium mobile and flagship platforms
Data center
AI Accelerator platform
Role Overview The team is currently seeking candidate specifically for SOC Infrastructure/NoC, Power and Performance Validation in pre-silicon emulation and post-silicon of industry-leading, next generation Premium-Tier Mobile & AI Accelerator platform. An adecuado candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture, performance and power.
Roles & Responsibilities Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in
SOC Bandwidth, QoS, Latency and Throughput analysis
Minimum Requirements BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
5+ years of experience in silicon validation, or platform bring-up.
Interconnect architectures - NoCs, AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage




Solid expertise in various FIFO designs and related performance/functionality aspects
Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM
Thorough understanding of CPU and DDR concepts, Multimedia, GPU, Peripherals
System low power modes, Dynamic clock and voltage scaling operations, Interrupt architecture
Debug architecture - interactions with JTAG based debuggers, state dump scripts
In depth debugging experience for Complex HW and SW issues
Experience working with Perfmon architecture -performance counters, telemetry data, and hardware/software co-optimization.
Drive correlation between pre-silicon models, emulation platforms, and silicon performance measurements.
Evaluate AI inference and training workloads to ensure optimal throughput, latency, memory bandwidth, and power-performance efficiency.
Contribute to methodology development for performance characterization, benchmarking, and KPI tracking across product generations.
Create performance dashboards, reports, and technical reviews for leadership and cross-functional stakeholders.
Experience in embedded systems/expertise in C, C++, Python and assembly languages. Design and Implementation of drivers and test content
Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation
Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design
Familiarity in debug tools including JTAG and kernel debuggers




Preferred Qualification Strong understanding of computer architecture, AI/ML accelerators, memory hierarchy, cache coherency, and on-chip interconnects.
Knowledge of AI/ML workloads, tensor operations, matrix multiplication, transformer models, and large-scale inference systems.
Familiarity with System level debug, silicon bring-up
Minimum Qualifications Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [email protected] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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📌 SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff (Centro-Norte)
🏢 QUALCOMM
📍 Centro-Norte