Micron Technology, based in Mexico, is seeking a layout engineer to design leaf cells and sub-blocks for cutting-edge memory devices. You will apply meticulous IC layout methods and interpret DRC/LVS checks to ensure design accuracy.
The role requires a recent degree in Electronics or related fields, familiarity with Cadence VLE/VXL or Mentor Calibre, and collaboration across teams. English communication and a proactive mindset are essential for growth in the semiconductor industry.