Micron Technology is seeking a Layout Build engineer for our DRAM Team in Guadalajara, Mexico. You will lead analog, mixed-signal and full-block layout activities, collaborating with general peers across multiple projects.
Responsibilities include planning, area and time estimation, and ensuring timely delivery of high-quality layouts while applying Cadence VLE/VXL and Mentor Calibre tools to meet stringent design rules and performance goals.
#J-18808-Ljbffr
📌 Lead Analog Layout Engineer for AI/HPC Chips (Centro)
🏢 Micron
📍 Centro
Postulate a este anuncio
Muestra tus habilidades a la empresa, rellenar el formulario y deja un toque personal en la carta, ayudará el reclutador en la elección del candidato.