Company Description Array Architecture (ARRAY) is redefining the foundations of modern computing by redesigning the core rules underlying current technology. Building on proposed solutions to fundamental problems in the philosophy of mathematics, ARRAY is creating a new framework for computation and information theory that drives innovation.

The company focuses on non‑incremental advances that challenge today’s system architectures, AI models, encryption schemes, and chip designs, which are increasingly constrained by existing paradigms. Key innovations include patented Compute‑In‑Memory architectures, such as the Simple and Linear Fast Adder (SLFA) for efficient AI/ML, cryptography, and edge computing, and novel homomorphic encryption methods that reduce noise, latency, and energy usage. ARRAY collaborates with investors, partners, and technical talent to build the future of efficient, secure, and scalable computing.

Role Description This is a full-time, on-site ASIC Physical Design Engineer role based in Guadalajara, JAL. The engineer will be responsible for translating complex architectural and RTL specifications into optimized physical implementations, including floorplanning, placement, clock tree synthesis, routing, and timing closure for advanced CMOS technologies.

Day-to-day tasks include collaborating with logic and RTL design teams, performing static timing analysis, power and signal integrity analysis, and driving design-for-test (DFT) considerations in the physical flow.



The role involves running and debugging physical design tools, managing design constraints, ensuring compliance with foundry design rules, and supporting tape-out activities. The engineer will work closely with cross-functional teams to help realize Array Architecture’s compute-in-memory and encryption-focused innovations in silicon.

Qualifications

- Strong Logic Design background, with experience in digital circuit design, architecture understanding, and timing concepts.
- Hands-on Physical Design skills, including floorplanning, placement, clock tree synthesis, routing, static timing analysis, and sign-off for ASICs.
- Proficiency in RTL Design and RTL Coding, using hardware description languages such as Verilog/SystemVerilog or VHDL.
- Experience with Formal Verification techniques and tools to ensure functional correctness and equivalence between RTL and gate-level implementations.
- Familiarity with industry-standard EDA tools (e.g., Synopsys, Cadence, Siemens) for synthesis, place-and-route, and verification.
- Knowledge of low-power design techniques, signal and power integrity, and design-for-test (DFT) methodologies.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- Ability to work on-site in Guadalajara, JAL, collaborate effectively in cross-disciplinary teams, and communicate technical information clearly.

📌 ASIC Physical Design Engineer (Guadalajara)
🏢 Array Architecture
📍 Guadalajara