HCL Technologies Limited seeks a seasoned ASIC/SoC verification engineer with 5 to 7 years of hands-on experience.
The role demands strong UVM-based testbench development, SystemVerilog, and experience with SV coverage, assertions, and constrained-random testing.Candidates should have contributed to ASIC/SoC verification up to tapeout, and be proficient in C-based testbench components, C/SV TB development, and regression/coverage closure.
A bachelor's or master's in ECE/EE/VLSI is expected.
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