Design and develop critical analog, mixed‐signal, custom digital blocks, and support full‐chip level integration. Perform layout verification activities including LVS, DRC, antenna checks, quality reviews, and documentation. Ensure on‐time delivery of block‐level layouts that meet quality expectations. Lead planning, area/time estimation, scheduling, delegation, and execution across multiple concurrent projects. Mentor and guide developing team members during sub-block layout execution and review their work. Communicate effectively with integral engineering teams to ensure layout project success. Demonstrated ability in analog/custom layout design in advanced CMOS processes across various technology nodes (Planar, FinFET). Bachelor's, Master's, or equivalent experience in Electronics, VLSI Engineering, or a related field. Expertise with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.



Hands‐on experience creating layout for critical blocks such as temperature sensors, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers, etc. Strong understanding of analog layout fundamentals: matching, electromigration, latch‐up, coupling, crosstalk, IR‐drop, and parasitic effects. Ability to assess circuit‐layout interactions including speed, capacitance, power, and area. Proven ability to interpret design constraints and implement high‐quality layouts. Experience supporting multiple tape‐outs. Experience leading multiple layout projects and ensuring quality gates across development stages. Strong problem‐solving skills in physical verification of custom layouts.

📌 Pathfinding Senior Design Layout Engineer (San Pedro Tlaquepaque)
🏢 Micron Technology
📍 San Pedro Tlaquepaque