Candidates with 5 to 7 years experience is mandatory Good understanding of ASIC/So C life cycle Has participated in multiple ASIC/So C verification till tapeout stage UVM based testbench development 2. Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)." SV functional coverage, Assertions coding 1. Expertise & hands-on experience in OVM/UVM methodologies using SV 2. Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. C based TB development 1. Experience in developing TB components for SOC with C, SV 1. Experience in developing TB components, including functional coverage implementation and assertion coding 2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3. Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 4. Experience in SOC C based tests coding & debugging Gate Level Simulation Regressions, coverage analysis Experience in regression failure analysis Functional and Code Coverage closure participate in verification closure Experience in Perl/Shell scripting Education Degree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Languages: Proficiency in Verilog, System Verilog, and core concepts of UVM. Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens Questa Sim, Cadence Xcelium/Verdi). Protocols: Deep,



authoritative knowledge of high-speed protocols (e.g., SPI, I2 C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)." Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation. Key Responsibilities Candidates with 5 to 7 years experience is mandatory Good understanding of ASIC/So C life cycle Has participated in multiple ASIC/So C verification till tapeout stage UVM based testbench development 2. Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)." SV functional coverage, Assertions coding 1. Expertise & hands-on experience in OVM/UVM methodologies using SV 2. Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans. C based TB development 1. Experience in developing TB components for SOC with C, SV 1. Experience in developing TB components, including functional coverage implementation and assertion coding 2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic. 3. Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues. 4. Experience in SOC C based tests coding & debugging Gate Level Simulation Regressions,



coverage analysis Experience in regression failure analysis Functional and Code Coverage closure participate in verification closure Experience in Perl/Shell scripting Education Degree: Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field Core Technical Skills Languages: Proficiency in Verilog, System Verilog, and core concepts of UVM. Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens Questa Sim, Cadence Xcelium/Verdi). Protocols: Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2 C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)." Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation. At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first. HCLTech is a general technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026totaled $14.8billion. #J-18808-Ljbffr

📌 Senior design lead (Centro)
🏢 HCL Technologies
📍 Centro