- define system-level power management architecture and operating modes
- define cpu and cluster power states and their coordination mechanisms
- define reset flow architecture, including cold and warm reset sequencing and reset-power state interactions
- define pm policies, sequencing, and state transitions across the platform
- define hardware–firmware power management interfaces and compliance expectations
- define power management requirements and constraints to guide implementation teams
- align architecture, rtl, physical design, thermal, and firmware teams around a coherent pm strategy
- support silicon bring-up and post-silicon power behavior validation

required experience

- 7+ years in soc or cpu power management architecture
- direct experience with arm cpu power management architecture, including familiarity with arm power management specifications and compliance requirements (e.g., psci,



arm power state definitions, firmware coordination models)
- strong understanding of system-level power state management and hardware–firmware pm interaction
- solid understanding of power delivery constraints
- track record of cross-functional coordination across architecture, design, and firmware teams

preferred experience

- familiarity with low-power implementation flows (e.g., upf) and physical power considerations
- understanding of thermal management concepts and power-thermal interaction at system level
- high-performance or server-class cpu experience
- risc-v experience
- silicon bring-up and post-silicon tuning experience
- multi-generation architecture planning experience

#j-18808-ljbffr

📌 Power management architect (México)
🏢 AheadComputing
📍 México