Company:QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Job Summary:
Job description:
- Design and develop physical layouts for logic standard cells using industry-standard computer-aided design (CAD) tools, such as Cadence Virtuoso. This role involves leveraging scripting and algorithmic programming languages, including SKILL and Python, to support layout automation, optimization, and design efficiency.
- Perform comprehensive layout verification, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC).
- Collaborate closely with circuit designers to ensure layouts meet quality, performance, and reliability requirements.
- Maintain and manage layout databases using designated Design Management software.
- Engage with the engineering design team to understand design concepts, constraints, and project milestones; accurately and concisely communicate design status and track schedules.
- Proactively and independently identify and resolve design
- and PDK-related issues; clearly document and communicate solutions to layout and engineering stakeholders.
- Work closely with Circuit Designers and Mask Layout Designers across integral development sites, including the United States, Taiwan, and India.
- Demonstrate strong communication skills and effective teamwork while contributing efficiently within a globally distributed engineering team.
Minimum Qualifications:
- Associate’s degree or technical certificate in Computer Science, Mathematics, Electrical Engineering, or a related discipline.
- Foundational understanding of CMOS technology and integrated circuit (IC) design principles.
- Strong attention to detail with the ability to work effectively in a collaborative team environment.
Preferred Qualifications:
- Bachelor’s degree in Computer Science, Engineering, or a related field.
- Knowledge of parasitic effects and reliabilit