Dram Layout Design Engineer – Ip Layout & Verification Lead (Lagos de Moreno)

Dram Layout Design Engineer – Ip Layout & Verification Lead (Lagos de Moreno)

12 sep
|
3050 Micron Semiconductor Mexico, S.de R.L. de
|
Lagos de Moreno

12 sep

3050 Micron Semiconductor Mexico, S.de R.L. de

Lagos de Moreno

**** Micron Semiconductor Mexico, S.De R.L. de C.V. is seeking a DRAM Design Engineer to transform schematics into layouts for fabrication reticules.
Responsibilities include designing IP layouts, verifying layouts for quality, and ensuring timely project delivery.The adecuado candidate should have a Bachelor's in Electrical or Electronics Engineering and at least 3 years of experience in advanced CMOS layout design.
Strong problem-solving skills and proficiency with Cadence tools are essential.
#J-*****-Ljbffr

📌 Dram Layout Design Engineer – Ip Layout & Verification Lead (Lagos de Moreno)
🏢 3050 Micron Semiconductor Mexico, S.de R.L. de
📍 Lagos de Moreno

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