Descripción

Job Overview

Are you excited to start your career in SoC design verification and learn how next-generation chips are verified from simulation to silicon? We are looking for motivated early-career engineers to join our SoC Design Verification team and grow through hands-on technical experience, mentorship, and exposure to real-world semiconductor projects.

In this role, you will support verification and validation activities for advanced SoCs used in mobile, AI, high-performance computing, and cloud infrastructure products. You will learn to run tests, review logs and waveforms, debug failures, support regressions, use emulation platforms, and gain exposure to pre-silicon and post-silicon validation flows while working closely with experienced engineers.

Key Responsibilities – Pre-Si And Post-Si Verification

- Assist with execution of verification plans for SoC, subsystem, and IP-level features.
- Support SystemVerilog/UVM, C/C++, processor-based, and simulation-driven verification environments under technical guidance.
- Develop and run basic directed and constrained-random tests to validate functional requirements and expected use cases.
- Debug RTL, testbench, firmware, and integration issues using simulation logs, waveforms, traces, assertions, and coverage results with guidance from senior team members.
- Support validation and correlation activities to help ensure verification results align with system-level behavior.
- Support validation and silicon bring-up activities under guidance, including basic data collection, result review, and correlation with expected system behavior.
- Assist with low-level software and hardware debug using available platform debug tools, logs, and guidance from senior engineers.
- Use emulation platforms to run assigned tests, collect results, report failures, and support debug activities with cross-functional teams.
- Run regressions, review failures, track bugs, and contribute to functional, code, assertion, and scenario coverage closure.
- Support verification of SoC and IP features such as processors, interconnects, memory subsystems, high-speed interfaces, security,



performance, and power-management functionality.
- For Engineer level: execute assigned verification tasks, develop tests and checkers, debug failures, maintain regressions, and contribute to coverage closure.
- For Senior Engineer level: support feature/subsystem verification planning, assist with cross-team debug, help identify schedule and quality risks, and contribute to methodology and automation improvements.
- Contribute to reusable verification components, scripting automation, productivity improvements, and continuous improvement of verification processes.

Minimum Qualifications

- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 0–2+ years of relevant academic, internship, or industry experience in digital design, design verification, validation, or SoC-related work.
- Basic understanding of digital logic, RTL concepts, computer architecture, and SoC/IP fundamentals.
- Basic exposure to Verilog/SystemVerilog, C/C++, Python, shell scripting, or similar programming/scripting languages.
- Interested in learning design verification methodologies, including test development, simulation, regression, coverage, and debug flows.
- Ability to review logs, waveforms, test results, or debug data to help identify failures and support root-cause analysis.
- Strong learning mindset, problem-solving ability, communication skills, and willingness to work collaboratively in a technical team environment.

Preferred Qualifications *

- Strong foundation in digital design, computer architecture, RTL concepts, and SoC/IP-level verification fundamentals.
- Basic experience with design verification methodologies, including test planning, testbench development, stimulus generation,



checkers, assertions, and coverage analysis.
- Hands-on exposure to simulation-based debug using logs, waveforms, assertions, coverage reports, and regression results.
- Working knowledge of SystemVerilog, UVM, C/C++, scripting, or related verification and automation technologies.
- Understanding pre-silicon verification flows and basic familiarity with post-silicon validation concepts such as bring-up, silicon debug, failure triage, or correlation with simulation results.
- Exposure to silicon bring-up, post-silicon characterization, Vmin/Fmax analysis, power/thermal measurements, or PVT-based silicon correlation is preferred but not required.
- Familiarity with emulation platforms, JTAG-based debug, kernel debuggers, or cross-functional debug with DFT, DV, CAD, RTL, design, validation, and software teams is a plus.
- Ability to analyze failures, isolate root causes, document findings, and work collaboratively with design, verification, validation, software, and test teams.
- For Sr. Engineer candidates: demonstrated ability to own feature-level verification tasks, drive debug closure, mentor junior engineers, and communicate technical risks clearly to stakeholders.

Preferred Candidate Profile The adecuado candidate is a curious and motivated early-career engineer who enjoys solving technical problems, learning new tools, and working with others. we are looking for strong fundamentals, a willingness to learn, and genuine interest in SoC verification, debug, and silicon validation. Why Join Us?

This is a great opportunity to build a strong foundation in semiconductor design verification while contributing to next-generation Mobile and Data Center solutions.

You will work alongside experienced engineers, learn industry-standard verification and debug practices, and gain exposure to advanced technologies such as CPUs, memory subsystems, AI accelerators, wireless, and high-speed connectivity. The role is designed to help early-career engineers grow through practical assignments, collaboration, and continuous learning.

📌 SOC Design Verification Engineer– Pre-Si/Post-Si Verification (Tijuana)
🏢 North American Production Sharing
📍 Tijuana