Lead Principal Engineer, Layout Design (San Pedro Tlaquepaque)

Lead Principal Engineer, Layout Design (San Pedro Tlaquepaque)

06 sep
|
Micron
|
San Pedro Tlaquepaque

06 sep

Micron

San Pedro Tlaquepaque

Our vision is to transform how the world uses information to enrich life for_all_.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities:
- Lead and complete advanced IC layout development for complex analog, digital, and/or mixed-signal blocks
- Own layout architecture decisions, including floorplanning, power routing, clocking, and signal integrity
- Ensure layout compliance with foundry build rules, DFM, DRC/LVS, and reliability requirements
- Collaborate with circuit designers to optimize performance, area, yield, and power
- Drive methodology improvements, layout automation, and guidelines across projects
- Review and sign off critical layout deliverables and achievements
- Mentor and technically guide layout engineers at all experience levels
- Partner with cross-functional teams (PD, PI, CAD, Verification, Process, Manufacturing) to resolve complex build issues
- Support silicon debug,



failure analysis, and continuous improvement initiatives

Required Qualifications:
- Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field
- 10+ years of experience in IC layout development for advanced semiconductor technologies
- Strong expertise in full‑custom layout and hierarchical build methodologies
- Hands‑on experience with industry‑standard EDA tools (Cadence Virtuoso or equivalent)
- Deep understanding of DRC, LVS, DFM, EM/IR, ESD, and reliability concepts
- Proven ability to lead technically complex projects with mínimal supervision
- Excellent communication skills and ability to work across integral teams

Preferred Qualifications:
- Experience at advanced technology nodes (e.g., sub‑10nm, FinFET, or equivalent)
- Background in memory, high-speed interfaces, or high-performance logic
- Experience influencing layout standards, PDK feedback, or CAD f

📌 Lead Principal Engineer, Layout Design (San Pedro Tlaquepaque)
🏢 Micron
📍 San Pedro Tlaquepaque

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