nCompany:nnQUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIAnn## Job Area:nnEngineering Group, Engineering Group u003e ASICS EngineeringnnGeneral Summary:nnPDK/CAD Engineer - Physical Verification and Extraction DevelopmentnnAs a leading technology innovator, Qualcomm pushes the boundaries of whatu0027s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. nnIn this highly cross functional role, you will be part of the General Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain, and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state-of-the-art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs.



This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modify the existing ones. nnMinimum Qualifications:nnu2022 Bacheloru0027s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. nOR nMasteru0027s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. nOR nPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.nnPreferred Qualifications:nn * Expertise in Calibre/ICV/Pegasus runset coding for DRC/LVS/ERC/PERC/MPT/ESD/Latch-up/Antennan * Experience with developing and customization of the StarRC/

📌 PDK/CAD Engineer (Michoacán)
🏢 Qualcomm
📍 Michoacán