DRAM Layout Engineer – IP Layout & Verification (Centro)

06 sep

Micron Memory Malaysia Sdn Bhd

Centro

06 sep

Micron Memory Malaysia Sdn Bhd

Centro

Micron Technology, Inc. is seeking a DRAM Design Tech Layout Engineer in Tlaquepaque, Jalisco, Mexico.
You will translate schematics into layout suitable for fabrication reticles and work with Design and other engineering groups to apply various layout techniques for digital and analog circuits. Responsibilities include IP layout development, layout verification (LVS/DRC/EM), and ensuring on‑time delivery of high‑quality layouts.

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📌 DRAM Layout Engineer – IP Layout & Verification (Centro)
🏢 Micron Memory Malaysia Sdn Bhd
📍 Centro

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