04 sep
|
3050 Micron Semiconductor Mexico, S.de R.L. de
|
Lagos de Moreno
04 sep
3050 Micron Semiconductor Mexico, S.de R.L. de
Lagos de Moreno
3050 Micron Semiconductor Mexico, S.de R.L. de C.V. is seeking a DRAM Design Engineer to transform schematics into layouts for fabrication reticules. Responsibilities include designing IP layouts, verifying layouts for quality, and ensuring timely project delivery.
The idóneo candidate should have a Bachelor's in Electrical or Electronics Engineering and at least 3 years of experience in advanced CMOS layout design. Strong problem-solving skills and proficiency with Cadence tools are essential.
#J-18808-Ljbffr
📌 DRAM Layout Design Engineer – IP Layout & Verification Lead (Lagos de Moreno)
🏢 3050 Micron Semiconductor Mexico, S.de R.L. de
📍 Lagos de Moreno