04 sep
|
Micron Technology
|
México
04 sep
Micron Technology
México
Micron Technology is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced engineers, gain hands-on experience with floorplanning, placement, routing, and physical verification, and develop automation solutions to improve productivity and quality.
The role involves scripting with Python or Perl, collaborating across teams, and applying AI-supported development practices.
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📌 DRAM IP Layout Intern — Automation & Verification (México)
🏢 Micron Technology
📍 México