Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Intelligent and high potential of learning new topics. Regression and PVT testing Potency in reading C code, understanding code flow, code manipulation, and test iteration. Familiarity with logic design Post-Si test execution and data review Debug tools including JTAG and kernel debuggers Experience with post-silicon enabling and bring-up Familiarity with DDR interface, JEDEC spec, bus level view of transactions Emulation Build Validation Proven track record of hardware related debug. hands-on experience of debugging low level software and hardware issues Familiarity with logic analyzer view of DDR bus

📌 DDR SVE engineer (Pachuca de Soto)
🏢 Qualcomm
📍 Pachuca de Soto