As a leading technology innovator, The Company pushes the boundaries of what’s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As an ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. The Company Engineers collaborate with cross-functional groups to determine product execution path.
The Integral SoC Power team is currently seeking candidate whose primary role is to implement and validate low power design intent requirements at the SoC-level. The role also expands to power analysis and projection of SoC Use Case power. The candidate will work with frontend teams from RTL, DFT, Synthesis, Design Verification and Physical Design during the SoC development. Also the candidate will have the opportunity to work with IP designers, power target (Chipset/SW) teams, and Post-Silicon test teams to jointly ensure power intent design requirements and power projections are fully validated.
QUALIFICATIONS: Bachelor's degree in Electrical or Computer Engineering plus:
Knowledge in SoC (ASIC) frontend development: Logic design, RTL coding, verification, synthesis, and timing closure
Power-aware implementation flow, including UPF/CPF/Conformal Low Power Check (CLP)
Scripting - Perl/Tcl/Python




PREFERRED QUALIFICATIONS: Bachelor's or Master's degree in Electrical/Electronics or Computer Engineering
Experience with/in: Familiarity of overall SoC Design Infrastructure – DDR, Busses, CPUs, I/Os and DFT Components
Familiarity of power islands, power gating, power sequencing and multi-voltage domain design
Responsibilities/Duties: Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent design at SoC level
Generate and validate power intent design (UPF) at SoC levelusing tools like CLP
Review designs and guide IP designers′s power intent design ensuring it meets SoC level low power implementation requirements
Work with design verification in validating low power design featurs at SoC and IP level.
Collaborate with company CAD and vendor to enhance existing power flows and tools
Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent QA
Execute power-aware implementation flow, including UPF/CPF/Conformal Low Power Check
Review IP design's power features and power budgets/estimates
Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone
Perform power analysis/projection of SoC baseline powerand deliver SoC power models to chipset
Execute power simulation/analysis tool (PtPx/PowerArtist)

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