DRAM IP Layout Intern: Design & Automation (Centro)

DRAM IP Layout Intern: Design & Automation (Centro)

29 ago
|
Micron Technology
|
Centro

29 ago

Micron Technology

Centro

Micron Technology, Inc in Mexico is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work with experienced layout engineers on floorplanning, placement, routing, and physical verification.
You will also explore automation via scripting and AI-supported development to improve productivity and design quality, with opportunities to learn EDA tools such as Cadence or Synopsys.

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📌 DRAM IP Layout Intern: Design & Automation (Centro)
🏢 Micron Technology
📍 Centro

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