Micron Technology in Mexico invites applications for a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will work alongside experienced engineers on floorplanning, placement, routing, and physical verification, while exploring automation and AI-supported tooling.
Idóneo candidates are pursuing a Bachelor’s degree in Electrical or Computer Engineering with graduation planned for December 2027 and have Python or
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📌 DRAM IP Layout Intern — AI-Driven Automation (México)
🏢 Micron
📍 México