Req ID: JR93196 Principal Layout Engineer Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description At Micron, we transform how the world uses information to enrich life for all. As a general leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing. Micronu2019s Interface Pathfinding team bridges corporate strategy and engineering execution through forwardu2011looking investigation and development of energyu2011efficient bandwidth solutions. The team identifies, evaluates, and drives performanceu2011scaling opportunities (3u20135 year horizon) through innovative circuit, signaling, packaging, and interconnect solutionsu2014all within a culture of diligent, continuous learning. Responsibilities
* Contribute to new product development by supporting the design, layout, and optimization of critical analog and mixedu2011signal circuits using comprehensive modeling.
* Drive the layout process including flooru2011planning, placement, and routing activities.
* Support design validation via testu2011chip preparation, reticle experiments, and required tapeu2011out revisions.
* Verify layout quality using DRC, LVS, and other vendor-supplied or internal verification tools.




* Deliver highu2011quality blocku2011level layouts on schedule.
* Collaborate across fields, including Signal Integrity, Circuit and Chip Design, and Packaging Ru0026 D. Minimum Qualifications
* 8+ years of layout experience, including multiple design tapeu2011outs.
* Proficiency in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
* Proven success in analog and/or highu2011speed I/O circuit layout design and flooru2011planning.
* Strong understanding of analog layout fundamentals: matching, shielding, coupling, crossu2011talk, electromigration, latchu2011up, dummy elements, IR drop, and parasitic impacts on area/power/performance.
* Experience with SPF analysis/simulation and layout modification for performance optimization.
* Demonstrated expertise in physical verification of custom layouts.
* Basic understanding of CMOS processes.
* Strong written and verbal communication skills. Preferred Qualifications
* Ability to work collaboratively within the broader Pathfinding and Strategy team.
* Flexibility to support a variety of technical areas as needed. Layout/Mask Designer E5 Relocation Level: TBD Before Getting Started
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📌 Principal layout engineer (Chihuahua)
🏢 Micron Technology
📍 Chihuahua