B. S/M. S. degree in Electrical Engineering, Computer Science. 1-2 years of experience in related fields. Strong programming skills in Python Hands-on experience with static timing analysis (STA) tools, e.g., Prime Time and Tempus Experience with place & route tools and have a good understanding of the ASIC RTL-GDSII design flow is a plus Critical thinking with good software architecture understanding to develop platforms at scale Familiarity with Gen AI models (e.g., LLMs such as GPT, Liama, etc.) and their application in real-world solutions, such as chatbots, etc. Experience designing and developing agentic AI systems Experience with version control tools like Perforce or Git a plus Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR Ph D in Science, Engineering, or related field.

📌 Senior asic methodology engineer (San Luis Potosí)
🏢 Qualcomm
📍 San Luis Potosí