Req ID: JR96284 PRINCIPAL ENG-HIG-HBM-LAYOUT Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: For more than 45 years, Micron Technology, Inc. has redefined innovation with the worldu2019s most advanced memory and semiconductor technologies. Weu2019re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.
We are looking for Layout Design Principal engineer at our Micron Technologyu2019s HBM Team in Guadalajara, Mexico. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high-performance computing solution, High Bandwidth Memory. As a Layout Design Engineer, you will be collaborating with peer teams crossing Micron integral footprint, in a multiple projects-based environment. Responsibilities:
* Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.
* Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
* Responsible for on-time delivery of block-level layouts with acceptable quality.
* Will be leading planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.
* Guide junior team-members in their execution of Sub block-level layouts u0026 review their work.




* Effectively communicating with Global engineering teams to assure the success of layout project. Minimum Qualification:
* 10+ yearsu0027 experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, Fin FET).
* BE or MTech in Electronic/VLSI Engineering, or related.
* Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must.
* Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,
* Knowledge of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.)
* Understanding layout effects on the circuit such as speed, capacitance, power and area etc.
* Ability to understand design constraints and implement high-quality layouts. Preferred qualifications:
* Multiple Tape out support experience will be an added advantage.
* Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development.
* Excellent command and problem-solving skills in physical verification of custom layout. Semiconductor Design Engineer 5 Relocation Level: TBD Before Getting Started
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📌 Principal eng-hig-hbm-layout (Irapuato)
🏢 Micron Technology
📍 Irapuato