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Company: QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA ## Job Area: Engineering Group, Engineering Group u003e ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whatu0027s possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/So C) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Design adaptive power management controller, on-chip sensor controller and digital power meter. u00b7 Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks. u00b7 Work closely with technology/circuit design team to close IP block specification/requirement. u00b7 Work closely with verification/physical design team to complete the IP design implementation. u00b7 Support So C team to integrate low power / power management IP solution into wireless So C chips and front-end design flows. u00b7 Work closely with system/software/test team to enable the low power feature in wireless So C product. u00b7 Work closely with system/software/test team to enable functional safety feature in automotive So C product. u00b7 Create/Enhance low power methodologies covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues. u00b7 Provide feedback for low-power chip and system architecture. u00b7 Understand and perform block u0026 chip-level power analysis.



u00b7 Understand and create block-level power models. Minimum Qualifications: u2022 Bacheloru0027s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Masteru0027s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
Ph D in Science, Engineering, or related field. Minimum Qualification u00b7 3 years of experience doing low power digital ASIC design. u00b7 Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA. u00b7 Familiar with scripting languages like Python, Perl, TCL u00b7 Understanding of electrical engineering concepts, circuit analysis and logic design skills. Preferred Qualifications u00b7 Previous experience in AVS (adaptive voltage scaling) desired. u00b7 Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired. u00b7 Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc. u00b7 Good understanding of So C architecture/micro-architecture. u00b7 Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus. u00b7 Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments. u00b7 Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap. Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail

📌 Low power design/methodology engineer (Culiacán Rosales)
🏢 Qualcomm
📍 Culiacán Rosales